chiptools.core.project module

class chiptools.core.project.Project(root='/home/nerdboy/src/chiptools/docs')

Bases: object

add_config(name, value, force=False)

Add a configuration key, value mapping for the project.

add_config_dict(**kwargs)

Add a configuration dictionary of key, value mappings for the project.

add_constraints(path, **attribs)

Add the given constraints file to the project.

add_file(path, library='work', **attribs)

Add the given file to the project.

add_files(root, library='work', pattern='*.*', **attribs)

Add all files in the given directory to the project. The optional pattern can be used to filter which paths are added.

add_generic(name, value)

Add a generic key, value mapping for the project.

add_unittest(path, **attribs)

Add the given TestSuite file to the project.

compile(tool_name=None)

Compile the libraries and files loaded into the Project. The Simulation tool that is used is determined by the tool_name input if supplied, otherwise the Project configuration : ‘simulator’ tool name will be used instead.

get_all_tool_argument_keys(tool_name)

Return all optional tool argument keys attached to this file for the given tool_name. The list returned by this method can be used to determine which tool arguments are available for the tool_name.

get_available_simulators()

Get a dictionary of the Simulators available on this system. Return a dictionary of tool_name : tool_instance where tool_name is a string name and tool_instance is a Simulator instance.

get_available_synthesisers()

Get a dictionary of the Synthesisers available on this system. Return a dictionary of tool_name : tool_instance where tool_name is a string name and tool_instance is a Synthesiser instance.

get_constraints()

Return a list of Constraint objects that have been added to the project.

get_files()

Return a list of File objects that have been added to the Project. The order in which the files appear in the list matches the order in which they were added to the project.

get_fpga_part()

Return the FPGA part to be used for synthesis.

get_generics()

Return a dictionary of (generic : setting) where generic is the string name of a HDL port generic and setting is the value to assign to the port generic. The port value can be a string, integer or boolean type.

get_libraries()

Return a dictionary of libname, [file_list] where libname is a string indicating a library name and [file_list] is a list of File objects that have been added to the library.

get_reporter()

Return function pointer to a reporter function that is executed after a synthesis run.

get_simulation_directory()

Return the path to the simulation directory where all simulation outputs will be stored.

get_simulation_tool_name()

Return the name of the simulation tool to use for simulation.

get_simulator_library_dependencies(tool_name)

Return a dictionary of library_name : path where both are strings and the library_name defines a simulation library dependency name and path provides the path to the dependency. Simulation libraries for the given simulation tool name are returned.

get_synthesis_directory()

Return the path to the synthesis directory where all synthesis outputs will be stored.

get_synthesis_fileset()

Return a dictionary of {lib : [file_a, file_b]} where lib is a string indicating the name of the library and [file_a, file_b] is a list of File objects that has been filtered to contain only files that have their .synthesise attribute set.

get_synthesis_tool_name()

Return the name of the synthesis tool to use for synthesis.

get_system_config_path()

Return a path string indicating the location of the .chiptoolsconfig configuration file.

get_tests()

Return a list of files implementing TestSuite objects.

get_tool_arguments(tool_name, flow_name)

Return the optional tool arguments attached to this file for the given tool_name and flow_name. If the tool or flow are not present in the optional arguments then return an empty string. Multiple spaces in the tool argument string are merged into a single space.

initialise(root='/home/nerdboy/src/chiptools/docs')

load_project(path)

Initialise this project instance using the project file supplied by path.

run_preprocessors()

Execute any Preprocessors attached to Files currently loaded into the Project. A preprocessor can be used to modify the contents of the file prior to simulation or synthesis.

run_tests(ids=None, tool_name=None)

Run the Project unit tests. The ids input is an iterable containing integer IDs referencing test cases from the test suite. If ids is None all tests in the test suite will be executed, otherwise the ids will be used to select which tests in the test suite are run.

The Simulation tool that is used is determined by the tool_name input if supplied, otherwise the Project configuration : ‘simulator’ tool name will be used instead.

set_cache_path(cache_path)

simulate(library, entity, tool_name=None, **kwargs)

Simulate the Project using the given library and entity as a top level. The Simulation tool that is used is determined by the tool_name input if supplied, otherwise the Project configuration : ‘simulator’ tool name will be used instead.

synthesise(library, entity, tool_name=None, fpga_part=None)

Synthesise the Project using the given library and entity as a top level. The synthesis tool that is used is determined by the tool_name input if supplied, otherwise the Project configuration : ‘synthesiser’ tool name will be used instead.

write_designtree_png(path, root)

chiptools.core.project.load_tests(path, simulation_path)

Import the test shim python module given by path and return a collection of Unittest classes for each of the tests found in the shim