chiptools.parsers.vhdl module

class chiptools.parsers.vhdl.Component(entity, instance=None, library=None)[source]

Bases: object

COMPONENT_RE = re.compile("\n        \\b                                  # Word boundary\n        component                           # Component keyword\n        \\s*                                 # Optional whitepsace\n  , re.IGNORECASE|re.VERBOSE)
INSTANCE_RE = re.compile("\n        \\b                                  # Word boundary\n        (?P<ident>\\w+)                      # Identifier\n        \\s*                                 # Optional whitespace\n        , re.IGNORECASE|re.VERBOSE)
classmethod get_all_definitions(data, library)[source]
classmethod get_all_references(data, binding_indications=None)[source]
class chiptools.parsers.vhdl.Configuration(name, entity, library='work')[source]

Bases: object

CONFIGURATION_RE = re.compile("\n        \\b                                  # Word boundary\n        configuration                       # Component keyword\n        \\s+                                 # At least one whitespace, re.IGNORECASE|re.VERBOSE)
classmethod get_all_definitions(data, library)[source]
class chiptools.parsers.vhdl.Entity(name, library='work')[source]

Bases: object

ENTITY_START_RE = re.compile("\n        \\b              # Word boundary\n        entity          # 'Entity' keyword\n        \\s+             # 1 or more whitespace\n        (?P<ident>\\w+)  # Mandatory identifier\n        \\s+ , re.IGNORECASE|re.VERBOSE)
classmethod get_all_definitions(data, library)[source]
classmethod get_all_references(data, libraries)[source]

Entity references are made by direct instantiation or by a component instantiation via a component definition. Embedded configurations can be used to make a component instantiation reference a entity directly.

class chiptools.parsers.vhdl.Function(name, library='work')[source]

Bases: object

REGEX = re.compile('\n        \\s*\n        function\n        \\s+\n        (?P<ident>\\w+)\n        \\s*\n        (?:\\([^;]*)?\n        \\s*\n        return\n        \\s*\n        (?:\\w+)\n        \\s+\n        is\n , re.IGNORECASE|re.VERBOSE)
classmethod get_all_definitions(data, library='work')[source]
class chiptools.parsers.vhdl.Package(name, library='work', unit=None)[source]

Bases: object

PACKAGE_START_RE = re.compile("\n        \\b                      # Word boundary\n        package                 # 'Package' keyword\n        \\s+                     # 1 or more whitespace\n        (?P<ident>\\w+)          # Ma, re.IGNORECASE|re.VERBOSE)
PACKAGE_USE_CLAUSES = "\n        \\b                      # Word boundary\n        use                     # use keyword\n        \\s*                     # Optional whitepsace\n        %(library)s             # Dynamic library name\n        \\.                      # '.' separator\n        (?P<module>\\w+)         # Module name\n        \\.                      # '.' separator\n        (?P<unit>all|\\w+)       # Part name ('all' or custom name)\n        \\s*                     # Optional whitespace\n        ;                       # Terminator\n        "
classmethod get_all_definitions(data, library='work')[source]
classmethod get_all_references(data, libraries)[source]
class chiptools.parsers.vhdl.ParsedVhdlFile(file_object)[source]

Bases: object

The ParsedVhdlFile class provides a high level wrapper for a source Vhdl file and provides convenient access to the design units referenced and declared by a file.

BINDING_INDICATION_RE = re.compile("\n        \\b                                      # Word boundary\n        for                                     # 'for' keyword\n        \\s+                                     # At least one wh, re.IGNORECASE|re.VERBOSE)
LIBRARY_RE = re.compile('\n        \\b                  # Word boundary\n        library             # Library keyword\n        \\s*                 # Optional whitespace\n        (?P<library>\\w+)    # Library name\n       , re.IGNORECASE|re.VERBOSE)
class chiptools.parsers.vhdl.Procedure(name, library='work')[source]

Bases: object

REGEX = re.compile('\n        \\s*\n        procedure\n        \\s+\n        (?P<id>\\w+)\n        \\s*\n        (?:\\([^;]*)?\n        \\s*\n        return\n        \\s*\n        (?:\\w+)\n        \\s+\n        is\n   , re.IGNORECASE|re.VERBOSE)
classmethod get_all_definitions(data, library='work')[source]
chiptools.parsers.vhdl.remove_comments(data)[source]

Return the supplied VHDL file data string, data, with all comments removed.