chiptools.wrappers.simulators.iverilog module

class chiptools.wrappers.simulators.iverilog.Iverilog(project, user_paths)

Bases: chiptools.wrappers.simulator.Simulator

compile_project(includes={})

This method stages files for compilation as we cannot perform compilation until additional runtime information such as generic assignments and the desired top-level entity are known. Incremental compilation is not supported by Icarus so the cache and library tracking are not used at all.

executables: List[str] = ['iverilog', 'vvp']

name = 'iverilog'

simulate(library, entity, gui=False, generics={}, includes={}, args=[], duration=None)

Compile and simulate the design.