chiptools.wrappers.synthesisers.ise module

class chiptools.wrappers.synthesisers.ise.Ise(project, user_paths, mode='manual')

Bases: chiptools.wrappers.synthesiser.Synthesiser

A ISE Synthesiser instance can be used to synthesise the files in the given Project using the XFLOW utility or individual Xst, Map, Par, Ngdbuild, Bitgen and Promgen tools provided in a base Xilinx ISE installation. The ISE synthesis flow can be set to either ‘manual’ flow where the individual ISE binaries are called in sequence or ‘xflow’ where the XFLOW utility is called (effectively the same thing). To use the ISE class it must be instanced with a Project and Options object passed as arguments, the ‘synthesise’ method may then be called to initiate the synthesis flow. In addition to running the synthesis flow, the ISE Synthesiser instance also uses a Reporter instance to filter the synthesis log messages for important information relating to the build.

When complete, the output files from synthesis will be stored in an archive bearing the name of the entity that was synthesised and a unique timestamp.

addConstraints(entity, synthesisDirectory)

Load the user constraints file path from the Project instance and generate a UCF file in the supplied synthesisDirectory directory where the synthesis tools are invoked.

executables: List[str] = ['xwebtalk', 'promgen', 'xst', 'map', 'par', 'ngdbuild', 'bitgen', 'xflow']

generate_programming_files(entity, working_directory)

Generate programming files using the output bitfile from the synthesis run. An MCS file is always generated, but additional files can be generated by adding ‘args_ise_promgen_<format>’ configuration items with the tool arguments to apply when calling promgen for that output format.

ise_bitgen(part, entity, working_directory)

Call the BITGEN binary, which accepts the following arguments:

Usage: bitgen [-d] [-j] [-b] [-w] [-l] [-m] [-t] [-n] [-u] [-a] [-r <bitFile>] [-intstyle ise|xflow|silent|pa] [-ise <projectrepositoryfile>] {-bd <BRAM_data_file> [tag <tagname>]} {-g <setting_value>} [-filter <filter_file[.filter]>] <infile[.ncd]> [<outfile>] [<pcffile[.pcf]>]

• entity is used to generate input and output file names

• workingDirectory is the working directory where the tool is invoked

ise_make_prom_file(fin, fout, working_directory, mode='mcs')

Generate a programming file using the promgen tool, the user can supply arguments to this flow stage with args_ise_promgen_<mode>.

ise_manual_flow(projectFilePath, part, entity, generics, workingDirectory, reportDirectory, exportDirectory)

Execute the manual ISE tool flow in the following order: #. XST #. NGDBUILD #. MAP #. PAR #. BITGEN

Refer to the individual documentation for these tools for more information.

ise_map(part, entity, working_directory)

Call the MAP binary, which accepts the following arguments:

map [-h] [-p partname] (infile[.ngd]) [-o (outfile[.ncd])] http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/devref.pdf

• part is passed to the -p input parameter

• entity is used to generate output file names

• workingDirectory is the working directory where the tool is invoked

ise_ngdbuild(part, entity, working_directory)

Call the NGDBUILD binary, which accepts the following arguments:

Usage: ngdbuild [-p <partname>] {-sd <source_dir>} {-l <library>} [-ur <rules_file[.urf]>] [-dd <output_dir>] [-r] [-a] [-u] [-nt timestamp|on|off] [-uc <ucf_file[.ucf]>] [-aul] [-aut] [-bm <bmm_file[.bmm]>] [-i] [-intstyle ise|xflow|silent] [-quiet] [-verbose] [-insert_keep_hierarchy] [-filter <filter_file[.filter]>] <design_name> [<ngd_file[.ngd]>]

• entity is used to generate input and output file names

• -sd is set to workingDirectory

• -p is set to part

• workingDirectory is the working directory where the tool is invoked

ise_par(entity, working_directory)

Call the PAR binary, which accepts the following arguments:

par [-ol std|high] [-pl std|high] [-rl std|high] [-xe n|c] [-mt on|off|1| 2|3|4] [-t <costtable:1,100>] [-p] [-k] [-r] [-w] [-smartguide <guidefile[.ncd]>] [-x] [-nopad] [-power on|off|xe] [-act ivityfile <activityfile[.vcd|.saif]>] [-ntd] [-intstyle ise|xflow|silent|pa] [-ise <projectrepositoryfile>] [-filter < filter_file[.filter]>] <infile[.ncd]>

<outfile> [<constraintsfile[.pcf]>]

• entity is used to generate output file names

• workingDirectory is the working directory where the tool is invoked

ise_promgen(fin, fout, working_directory, args=None)

Call the promgen binary, which accepts the following arguments:

Usage: promgen [-b] [-spi] [-p mcs|exo|tek|hex|bin|ieee1532|ufp] [-o <outfile> {<outfile>}] [-s <size> {<size>}] [-x <xilinx_prom> {<xilinx_prom>}] [-c [<hexbyte>]] [-l] [-w] [-bpi_dc serial|parallel] [-intstyle ise|xflow|silent] [-t <templatefile[.pft]>] [-z [<version:0,3>]] [-i <version:0,3>] [-data_width 8|16|32] [-config_mode selectmap8|selectmap16|selectmap32] {-ver <version:0,3> <file> {<file>}} {-u <hexaddr> <file> {<file>}} {-d <hexaddr> <file> {<file>}} {-n <file> {<file>}} {-bd <file> [start <hexaddr>] [tag <tagname> {<tagname>}]} {-bm <file>} {-data_file up|down <hexaddr> <file> {<file>}} [-r <promfile>]

• fin is passed to the <file> input parameter

• fout is passed to the -o input parameter

• workingDirectory is the working directory where the tool is invoked

ise_webtalk_off()

Call the xwebtalk binary with the -user off switch to disable WebTalk

ise_xflow(projectFilePath, part, entity, generics, workingDirectory, reportDirectory, exportDirectory)

Call the XFLOW binary, which accepts the following arguments:

xflow [-p partname] [flow type] [options file[.opt]] [xflow options] design_name

XFLOW Flow Types:

Create a bitstream for FPGA device configuration using a routed design. -config option_file

Create a file that can be used for formal verification of an FPGA design. -ecn option_file

Incorporate logic from the design into physical macrocell locations in a CPLD -fit option_file

Generate a file that can be used for functional simulation of an FPGA or CPLD design -fsim option_file

Implement the design and output a routed NCD file -implement option_file[fast_runtime.opt, balanced.opt, high_effort.opt]

Create a file that can be used to perform static timing analysis of an FPGA design -sta option_file

Synthesise the design for implementation in an FPGA, for fitting in a CPLD or for compiling for functional simulation. -syth option_file[xst_vhdl.opt/xst_verilog.opt/xst_mixed.opt]

Generate a file that can be used for timing simulation of an FPGA or CPLD design. -tsim option_file

ise_xst(part, entity, generics, working_directory)

Generate an XST settings file and call the XST binary

makeProject(projectFilePath, fileFormat='mixed')

Generate a Xilinx ISE project file listing source files with their filetypes and libraries. ISE requires a project file to be written using the following format:

Where hdl_language specifies whether the designated HDL source file is written in VHDL or Verilog, compilation_library specifies the library where the HDL is compiled and source_file specifies the path to the source file. This method generates an appropriate file from the project data that has been loaded into the ISE Synthesiser instance.

name = 'ise'

synthesise(library, entity, fpga_part=None)

Synthesise the target entity in the given library for the currently loaded project. The following steps are performed during synthesis:

• Create synthesis directories

• Generate an ISE project file

• Generate an ISE UCF constraints file

• Invoke XFLOW or the flow tools individually with appropriate command line arguments

• Generate reports

• Archive the outputs of the synthesis flow