chiptools.wrappers.synthesisers.quartus module

class chiptools.wrappers.synthesisers.quartus.Quartus(project, user_paths)

Bases: chiptools.wrappers.synthesiser.Synthesiser

A Quartus Synthesiser instance can be used to synthesise the files in the given Project using the quartus_sh utility provided in a base Altera Quartus installation. The Quartus synthesis flow follows the following steps:

• Create synthesis directories

• Create a project TCL file listing FPGA part, source files and any constraints * Invoke quartus_sh

• Archive the outputs

In addition to running the quartus_sh synthesis flow, the Quartus Synthesiser instance also uses a Reporter instance to filter the synthesis log messages for important information relating to the build.

When complete, the output files from synthesis will be stored in an archive bearing the name of the entity that was synthesised and a unique timestamp.

exec_quartus_sh(projectFilePath, workingDirectory)

Invoke quartus_sh using the TCL file pointed to by projectFilePath using the given workingDirectory as a working directory.

quartus_sh uses the following command line arguments:

quartus_sh
-f=<argument file>
-h
-s
-t=<script file>
-v
--64bit
--archive
--determine_smart_action
--dse
--dtw
--flow
--help[=<option|topic>]
--lower_priority
--prepare
--qboard
--qhelp
--qinstall
--qslave
--relcon
--restore
--script=<script file>
--set
--shell
--simlib_comp
--tcl_eval=<tcl command>
--version

executables: List[str] = ['quartus_sh', 'quartus_cpf']

generate_programming_files(entity, working_directory)

Convert programming files using the quartus_cpf utility using user defined arguments supplied in the project configuration. User defined arguments should be supplied via configuration items using the following naming convention: ‘args_quartus_cpf_<format>’. If no configuration items matching this naming convention are provided then no additional programming files will be generated.

makeProject(projectFilePath, files, constraints, part, generics, workingDirectory, entity)

Generate a TCL file that is compatible with the quartus_sh API to allow the source files in the supplied files list to be built using the quartus_sh utility. The following items are inserted into the resulting TCL file:

• Relevant TCL imports (::quartus::project, ::quartus::flow)

• Entity

• FPGA Part

• Source Files

• Synthesis Generics (for the top level entity)

• Constraints (as a TCL script appended to the project TCL file)

• TCL commands to execute synthesis flow

The TCL file to be written will be stored at the given projectFilePath filepath.

name = 'quartus'

synthesise(library, entity, fpga_part=None)

Synthesise the target entity in the given library for the currently loaded project. The following steps are performed during synthesis:

• Create synthesis directories

• Create a project TCL file listing FPGA part, source files and any constraints * Invoke quartus_sh

• Generate reports

• Archive the outputs

tcl_add_file(fileObject)

Return the Quartus API TCL command string: set_global_assignment [VHDL_FILE/VERILOG_FILE] <fileObject.path> -library <fileObject.library>

tcl_project_close()

Return the Quartus API TCL command string: project_close [-dont_export_assignments]

tcl_project_new(entity)

Return the Quartus API TCL command string: project_new [-family <family>] [-overwrite] [-part <part>] [-revision <revision_name>] <project_name>

tcl_set_generic(name, value)

Return the Quartus API TCL command string: set_parameter -name <name> <value>

tcl_set_part(part)

Return the Quartus API TCL command string: set_global_assignment -name DEVICE <part>

tcl_set_top_level_entity(entity)

Return the Quartus API TCL command string: set_global_assignment -name TOP_LEVEL_ENTITY <entity>