chiptools.wrappers.synthesisers.vivado module

class chiptools.wrappers.synthesisers.vivado.Vivado(project, user_paths)

Bases: chiptools.wrappers.synthesiser.Synthesiser

add_constraints()

add_sources()

executables: List[str] = ['vivado']

name = 'vivado'

report_clock_utilization(path)

report_drc(path)

report_timing(path)

report_timing_summary(path)

report_utilization(path)

synth_design(name, part, entity, generics, *args)

synthesise(library, entity, fpga_part=None)

Synthesise the target entity in the given library for the currently loaded project.

vivado_name = 'vivado'

write_bitstream(path)

write_checkpoint(path)

write_tcl(command)

Append the given TCL command to the project TCL script. The command will be wrapped in a try: catch block so that Vivado can exit gracefully in the event of an error.